Method for efficient large-scale cryogenic characterization of CMOS technologies

TL;DR

This paper presents a new efficient method for large-scale cryogenic characterization of CMOS transistors, enabling rapid data collection crucial for quantum computing hardware development.

Contribution

The authors developed a system using on-die multiplexers for bulk DC measurements of transistors at 4.2 K, significantly improving characterization efficiency.

Findings

Enabled characterization of thousands of devices simultaneously

Reduced measurement setup complexity at cryogenic temperatures

Facilitated creation of cryo-compatible process design kits

Abstract

Semiconductor integrated circuits operated at cryogenic temperature will play an essential role in quantum computing architectures. These can offer equivalent or superior performance to their room-temperature counterparts while enabling a scaling up of the total number of qubits under control. Silicon integrated circuits can be operated at a temperature stage of a cryogenic system where cooling power is sufficient ($\sim$3.5+ K) to allow for analog signal chain components (e.g. amplifiers and mixers), local signal synthesis, signal digitization, and control logic. A critical stage in cryo-electronics development is the characterization of individual transistor devices in a particular technology node at cryogenic temperatures. This data enables the creation of a process design kit (PDK) to model devices and simulate integrated circuits operating well below the minimum standard temperature ranges covered by foundry-released models (e.g. -55 {\deg}C). Here, an efficient approach to the characterization of large numbers of components at cryogenic temperature is reported. We developed a system to perform DC measurements with Kelvin sense of individual transistors at 4.2 K using integrated on-die multiplexers, enabling bulk characterization of thousands of devices with no physical change to the measurement setup.