Scatter-Gather DMA Performance Analysis within an SoC-based Control System for Trapped-Ion Quantum Computing

TL;DR

This paper evaluates the latency and throughput of scatter-gather DMA on RFSoC devices to assess their suitability for control systems in trapped-ion quantum computing, focusing on high-bandwidth, low-latency data transfers.

Contribution

It provides an experimental analysis of SG-DMA performance on RFSoC hardware specifically for TIQC control applications, highlighting benefits and limitations.

Findings

SG-DMA achieves high throughput for large buffer descriptors

Latency varies with buffer size and payload

RFSoC architecture is promising for quantum control systems

Abstract

Scatter-gather dynamic-memory-access (SG-DMA) is utilized in applications that require high bandwidth and low latency data transfers between memory and peripherals, where data blocks, described using buffer descriptors (BDs), are distributed throughout the memory system. The data transfer organization and requirements of a Trapped-Ion Quantum Computer (TIQC) possess characteristics similar to those targeted by SG-DMA. In particular, the ion qubits in a TIQC are manipulated by applying control sequences consisting primarily of modulated laser pulses. These optical pulses are defined by parameters that are (re)configured by the electrical control system. Variations in the operating environment and equipment make it necessary to create and run a wide range of control sequence permutations, which can be well represented as BD regions distributed across the main memory. In this paper, we experimentally evaluate the latency and throughput of SG-DMA on Xilinx radiofrequency SoC (RFSoC) devices under a variety of BD and payload sizes as a means of determining the benefits and limitations of an RFSoC system architecture for TIQC applications.