A Multi-Expert Large Language Model Architecture for Verilog Code Generation

TL;DR

This paper presents MEV-LLM, a multi-expert large language model architecture that improves Verilog code generation by fine-tuning models on design complexity categories, resulting in higher quality outputs.

Contribution

The paper introduces a novel multi-expert LLM architecture for Verilog code generation that leverages specialized fine-tuning for different design complexities.

Findings

Increased percentage of syntactically correct Verilog code.

Enhanced functional correctness of generated Verilog outputs.

Demonstrated superiority over existing approaches.

Abstract

Recently, there has been a surging interest in using large language models (LLMs) for Verilog code generation. However, the existing approaches are limited in terms of the quality of the generated Verilog code. To address such limitations, this paper introduces an innovative multi-expert LLM architecture for Verilog code generation (MEV-LLM). Our architecture uniquely integrates multiple LLMs, each specifically fine-tuned with a dataset that is categorized with respect to a distinct level of design complexity. It allows more targeted learning, directly addressing the nuances of generating Verilog code for each category. Empirical evidence from experiments highlights notable improvements in terms of the percentage of generated Verilog outputs that are syntactically and functionally correct. These findings underscore the efficacy of our approach, promising a forward leap in the field of automated hardware design through machine learning.