Modeling Analog-Digital-Converter Energy and Area for Compute-In-Memory Accelerator Design

TL;DR

This paper introduces an open-source model that estimates the energy and area of ADCs in compute-in-memory accelerators, facilitating rapid architecture-level design space exploration by abstracting circuit details.

Contribution

The work presents a novel, architecture-level model for ADC energy and area estimation, enabling efficient exploration of design tradeoffs in CiM accelerators.

Findings

Model accurately predicts ADC energy and area based on architecture parameters

Enables fast exploration of design tradeoffs in CiM accelerators

Open-source implementation available for researchers

Abstract

Analog Compute-in-Memory (CiM) accelerators use analog-digital converters (ADCs) to read the analog values that they compute. ADCs can consume significant energy and area, so architecture-level ADC decisions such as ADC resolution or number of ADCs can significantly impact overall CiM accelerator energy and area. Therefore, modeling how architecture-level decisions affect ADC energy and area is critical for performing architecture-level design space exploration of CiM accelerators. This work presents an open-source architecture-level model to estimate ADC energy and area. To enable fast design space exploration, the model uses only architecture-level attributes while abstracting circuit-level details. Our model enables researchers to quickly and easily model key architecture-level tradeoffs in accelerators that use ADCs.