Chiplet Placement Order Exploration Based on Learning to Rank with Graph Representation

TL;DR

This paper introduces a graph-based learning to rank method to optimize chiplet placement order, significantly improving system temperature and wirelength in chiplet-based systems.

Contribution

It proposes a novel learning to rank approach with graph representation to determine optimal chiplet placement order, enhancing reinforcement learning placement strategies.

Findings

10.05% reduction in inter-chiplet wirelength

1.01% improvement in peak system temperature

outperforms traditional ordering methods

Abstract

Chiplet-based systems, integrating various silicon dies manufactured at different integrated circuit technology nodes on a carrier interposer, have garnered significant attention in recent years due to their cost-effectiveness and competitive performance. The widespread adoption of reinforcement learning as a sequential placement method has introduced a new challenge in determining the optimal placement order for each chiplet. The order in which chiplets are placed on the interposer influences the spatial resources available for earlier and later placed chiplets, making the placement results highly sensitive to the sequence of chiplet placement. To address these challenges, we propose a learning to rank approach with graph representation, building upon the reinforcement learning framework RLPlanner. This method aims to select the optimal chiplet placement order for each chiplet-based system. Experimental results demonstrate that compared to placement order obtained solely based on the descending order of the chiplet area and the number of interconnect wires between the chiplets, utilizing the placement order obtained from the learning to rank network leads to further improvements in system temperature and inter-chiplet wirelength. Specifically, applying the top-ranked placement order obtained from the learning to rank network results in a 10.05% reduction in total inter-chiplet wirelength and a 1.01% improvement in peak system temperature during the chiplet placement process.