Memory Sharing with CXL: Hardware and Software Design Approaches

TL;DR

This paper explores hardware and software strategies for enabling memory sharing using the emerging CXL standard, addressing protocol-specific challenges to improve memory utilization.

Contribution

It presents multiple approaches for memory sharing with CXL 2.0 and 3.0, considering hardware and software design challenges.

Findings

Proposed various hardware and software memory sharing approaches.

Analyzed challenges associated with CXL 2.0 and 3.0.

Discussed potential benefits for memory utilization.

Abstract

Compute Express Link (CXL) is a rapidly emerging coherent interconnect standard that provides opportunities for memory pooling and sharing. Memory sharing is a well-established software feature that improves memory utilization by avoiding unnecessary data movement. In this paper, we discuss multiple approaches to enable memory sharing with different generations of CXL protocol (i.e., CXL 2.0 and CXL 3.0) considering the challenges with each of the architectures from the device hardware and software viewpoint.