DE-HNN: An effective neural model for Circuit Netlist representation
Zhishang Luo, Truong Son Hy, Puoya Tabaghi, Donghyeon Koh, Michael, Defferrard, Elahe Rezaei, Ryan Carey, Rhett Davis, Rajeev Jain, Yusu Wang

TL;DR
This paper introduces DE-HNN, a novel neural network model that effectively represents circuit netlists as directed hypergraphs, enabling faster and more accurate predictions of chip design optimization outcomes.
Contribution
The paper proposes a new directed hypergraph neural network model, DE-HNN, tailored for circuit netlist data, addressing challenges of large size and long-range interactions, with proven universal approximation capabilities.
Findings
DE-HNN outperforms existing graph neural networks in predicting placement and routing outcomes.
The model effectively captures long-range dependencies in large netlist hypergraphs.
Source code and data are publicly available for reproducibility.
Abstract
The run-time for optimization tools used in chip design has grown with the complexity of designs to the point where it can take several days to go through one design cycle which has become a bottleneck. Designers want fast tools that can quickly give feedback on a design. Using the input and output data of the tools from past designs, one can attempt to build a machine learning model that predicts the outcome of a design in significantly shorter time than running the tool. The accuracy of such models is affected by the representation of the design data, which is usually a netlist that describes the elements of the digital circuit and how they are connected. Graph representations for the netlist together with graph neural networks have been investigated for such models. However, the characteristics of netlists pose several challenges for existing graph learning frameworks, due to the…
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Taxonomy
TopicsVLSI and Analog Circuit Testing · VLSI and FPGA Design Techniques · Integrated Circuits and Semiconductor Failure Analysis
