E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis

TL;DR

E-Syn introduces an e-graph based approach for logic synthesis that explores a broader design space, enabling significant improvements in delay and area metrics over traditional methods.

Contribution

This paper presents a novel e-graph based workflow for logic synthesis, enhancing exploration capabilities with technology-aware cost functions.

Findings

Achieves 15.29% delay reduction on average

Achieves 6.42% area reduction on average

Outperforms traditional AIG-based synthesis in experiments

Abstract

Logic synthesis plays a crucial role in the digital design flow. It has a decisive influence on the final Quality of Results (QoR) of the circuit implementations. However, existing multi-level logic optimization algorithms often employ greedy approaches with a series of local optimization steps. Each step breaks the circuit into small pieces (e.g., k-feasible cuts) and applies incremental changes to individual pieces separately. These local optimization steps could limit the exploration space and may miss opportunities for significant improvements. To address the limitation, this paper proposes using e-graph in logic synthesis. The new workflow, named Esyn, makes use of the well-established e-graph infrastructure to efficiently perform logic rewriting. It explores a diverse set of equivalent Boolean representations while allowing technology-aware cost functions to better support delay-oriented and area-oriented logic synthesis. Experiments over a wide range of benchmark designs show our proposed logic optimization approach reaches a wider design space compared to the commonly used AIG-based logic synthesis flow. It achieves on average 15.29% delay saving in delay-oriented synthesis and 6.42% area saving for area-oriented synthesis.