Concatenated Steane code with single-flag syndrome checks

TL;DR

This paper presents a fault-tolerant error correction protocol for the [[49,1,9]] concatenated Steane code, achieving high error suppression with low overhead and feasible implementation on planar layouts, outperforming certain codes under circuit-level noise.

Contribution

Develops a distance-preserving flag fault-tolerant error correction protocol for the [[49,1,9]] concatenated Steane code with minimal ancilla qubits and optimized syndrome extraction.

Findings

Pseudothreshold of 1.64e-3 for the [[49,1,9]] code.

Outperforms the [[61,1,9]] color code under circuit-level noise.

Feasible planar implementation with two ancilla qubits per generator.

Abstract

A fault-tolerant error correction (FTEC) protocol with a high error suppression rate and low overhead is very desirable for the near-term implementation of quantum computers. In this work, we develop a distance-preserving flag FTEC protocol for the [[49,1,9]] concatenated Steane code, which requires only two ancilla qubits per generator and can be implemented on a planar layout. We generalize the weight-parity error correction (WPEC) technique from [Phys. Rev. A 104, 042410 (2021)] and find a gate ordering of flag circuits for the concatenated Steane code which makes syndrome extraction with two ancilla qubits per generator possible. The FTEC protocol is constructed using the optimization tools for flag FTEC developed in [PRX Quantum 5, 020336 (2024)] and is simulated under the circuit-level noise model without idling noise. Our simulations give a pseudothreshold of $1.64 \times 10^{-3}$ for the [[49,1,9]] concatenated Steane code, which is better than a pseudothreshold of $1.43 \times 10^{-3}$ for the [[61,1,9]] 6.6.6 color code simulated under the same settings. This is in contrast to the code capacity model where the [[61,1,9]] code performs better.