I/O Transit Caching for PMem-based Block Device

TL;DR

This paper introduces Caiti, an I/O transit caching algorithm that enhances PMem-based block device performance by reducing stalls and improving throughput, addressing limitations of traditional BTT implementations.

Contribution

It proposes a novel I/O transit caching algorithm, Caiti, that improves performance of PMem block devices by optimizing cache evictions and direct writes.

Findings

Caiti achieves up to 3.6x performance improvement.

Caiti maintains block-level write atomicity.

The approach reduces I/O stalls significantly.

Abstract

Byte-addressable non-volatile memory (NVM) sitting on the memory bus is employed to make persistent memory (PMem) in general-purpose computing systems and embedded systems for data storage. Researchers develop software drivers such as the block translation table (BTT) to build block devices on PMem, so programmers can keep using mature and reliable conventional storage stack while expecting high performance by exploiting fast PMem. However, our quantitative study shows that BTT underutilizes PMem and yields inferior performance, due to the absence of the imperative in-device cache. We add a conventional I/O staging cache made of DRAM space to BTT. As DRAM and PMem have comparable access latency, I/O staging cache is likely to be fully filled over time. Continual cache evictions and fsyncs thus cause on-demand flushes with severe stalls, such that the I/O staging cache is concretely unappealing for PMem-based block devices. We accordingly propose an algorithm named Caiti with novel I/O transit caching. Caiti eagerly evicts buffered data to PMem through CPU's multi-cores. It also conditionally bypasses a full cache and directly writes data into PMem to further alleviate I/O stalls. Experiments confirm that Caiti significantly boosts the performance with BTT by up to 3.6x, without loss of block-level write atomicity.