A multiplexed control architecture for superconducting qubits with row-column addressing

TL;DR

This paper proposes a scalable multiplexed control architecture for superconducting qubits using shared row and column control lines, significantly reducing wiring complexity for large quantum processors.

Contribution

Introduction of a novel multiplexed control architecture with shared row and column lines enabling efficient parallel control of large qubit arrays.

Findings

Reduces control lines from N to approximately √N for N qubits.

Enables parallel delivery of control pulses at each row-column intersection.

Suitable for structured quantum circuits like error correction.

Abstract

In state-of-the-art superconducting quantum processors, each qubit is controlled by at least one control line that delivers control pulses generated at room temperature to qubits operating at millikelvin temperatures. While this strategy has been successfully applied to control hundreds of qubits, it is unlikely to be scalable to control thousands of qubits, let alone millions or even billions of qubits needed in fault-tolerance quantum computing. The primary obstacle lies in the wiring challenge, wherein the number of accommodated control lines is limited by factors, such as the cooling power, physical space of the cryogenic system, the control footprint area at the qubit chip level, and so on. Here, we introduce a multiplexed control architecture for superconducting qubits with two types of shared control lines, row and column lines, providing an efficient approach for parallel controlling $N$ qubits with $O(\sqrt{N})$ control lines. With the combination of the two-type shared lines, unique pairs of control pulses are delivered to qubits at each row-column intersection, enabling parallel qubit addressing. Of particular concern here is that, unlike traditional gate schemes, both single- and two-qubit gates are implemented with pairs of control pulses. Considering the inherent parallelism and the control limitations, the integration of the architecture into quantum computing systems should be tailored as much as possible to the specific properties of the quantum circuits to be executed. As such, the architecture could be scalable for executing structured quantum circuits, such as quantum error correction circuits.