Efficient FIR filtering with Bit Layer Multiply Accumulator

TL;DR

This paper introduces the Bit Layer Multiplier Accumulator (BLMAC), a novel method for efficient FIR filtering that eliminates multiplications by leveraging bit-level sparsity, and demonstrates its implementation on FPGA with promising performance.

Contribution

The paper presents a new BLMAC approach for FIR filtering, including a specialized FPGA implementation that significantly reduces computational complexity and resource usage.

Findings

BLMAC reduces the number of additions needed for FIR filtering.

The FPGA implementation achieves filtering rates of 1.4-3.4 Msamples/s.

Systematic generation and quantization of nearly 2 million FIR filters were performed.

Abstract

Bit Layer Multiplier Accumulator (BLMAC) is an efficient method to perform dot products without multiplications that exploits the bit level sparsity of the weights. A total of 1,980,000 low, high, band pass and band stop type I FIR filters were generated by systematically sweeping through the cut off frequencies and by varying the number of taps from 55 to 255. After their coefficients were quantized to 16 bits, applying the filter using a BLMAC required, on average, from ~123.3 to ~513.6 additions, depending on the number of taps. A BLMAC dot product machine, specialised for 127 taps FIR filters, was designed for AMD FPGAs. The design footprint is ~110 LUTs, including coefficient and sample storage and is able to apply the filter in ~232 clock cycles on average. This implies a filtering rate of 1.4-3.4 Msamples/s, depending on the FPGA family.