Less is More: Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
Chenhui Deng, Zichao Yue, Cunxi Yu, Gokce Sarar, Ryan Carey, Rajeev, Jain, Zhiru Zhang

TL;DR
This paper introduces HOGA, a scalable and generalizable attention-based model for circuit representation learning that outperforms traditional GNNs in accuracy and training efficiency across EDA tasks.
Contribution
HOGA employs hop-wise features and gated self-attention to improve scalability and generalization in circuit graph learning, addressing limitations of existing GNNs.
Findings
Reduces QoR prediction error by 46.76% compared to GNNs.
Improves functional reasoning accuracy by 10% on unseen netlists.
Training time decreases nearly linearly with more computing resources.
Abstract
While graph neural networks (GNNs) have gained popularity for learning circuit representations in various electronic design automation (EDA) tasks, they face challenges in scalability when applied to large graphs and exhibit limited generalizability to new designs. These limitations make them less practical for addressing large-scale, complex circuit problems. In this work we propose HOGA, a novel attention-based model for learning circuit representations in a scalable and generalizable manner. HOGA first computes hop-wise features per node prior to model training. Subsequently, the hop-wise features are solely used to produce node representations through a gated self-attention module, which adaptively learns important features among different hops without involving the graph topology. As a result, HOGA is adaptive to various structures across different circuits and can be efficiently…
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Taxonomy
TopicsLow-power high-performance VLSI design · Machine Learning and Algorithms · VLSI and Analog Circuit Testing
