Multi-junction surface ion trap for quantum computing

TL;DR

This paper presents a multi-junction surface ion trap design that reduces power dissipation and heating rates, advancing scalable quantum computing architectures with integrated photonics and cryogenic operation.

Contribution

It introduces a novel trap design with a raised RF electrode that minimizes power dissipation and demonstrates heating rate measurements across various conditions.

Findings

Reduced power dissipation through raised RF electrode design

Lower heating rates observed across different motional frequencies

Effective operation with integrated photonics at cryogenic temperatures

Abstract

Surface ion traps with two-dimensional layouts of trapping regions are natural architectures for storing large numbers of ions and supporting the connectivity needed to implement quantum algorithms. Many of the components and operations needed to fully exploit this architecture have already been demonstrated, including operation at cryogenic temperatures with low heating, low excitation transport, and ion control and detection with integrated photonics. Here we demonstrate a trap that addresses the scaling challenge of increasing power dissipation as the RF electrode increases in size. By raising the RF electrode and removing most of the insulating dielectric layer below it we reduce both ohmic and dielectric power dissipation. We also measure heating rates across a range of motional frequencies and for different voltage sources in a trap with a raised RF electrode but solid dielectric.