Mitigating variability in epitaxial-heterostructure-based spin-qubit devices by optimizing gate layout

TL;DR

This paper investigates how optimizing gate layouts, especially with tip-shaped gates, can reduce variability caused by charge traps in spin qubit devices, improving their scalability.

Contribution

It introduces a novel gate layout design that maximizes interface coverage, reducing variability in spin qubit devices compared to traditional planar layouts.

Findings

Tip-shaped gates outperform planar layouts in certain regimes.

Maximizing gate coverage reduces charge trap effects.

Screening by metal gates mitigates variability.

Abstract

The scalability of spin qubit devices is conditioned by qubit-to-qubit variability. Disorder in the host materials indeed affects the wave functions of the confined carriers, which leads to variations in their charge and spin properties. Charge disorder in the amorphous oxides is particularly detrimental owing to its long-range influence. Here we analyze the effects of charge traps at the semiconductor/oxide interface, which are generally believed to play a dominant role in variability. We consider multiple random distributions of these interface traps and numerically calculate their impact on the chemical potentials, detuning and tunnel coupling of two adjacent quantum dots in SiGe heterostructure. Our results highlight the beneficial screening effect of the metal gates. The surface of the heterostructure shall, therefore, be covered as much as possible by the gates in order to limit variability. We propose an alternative layout with tip-shaped gates that maximizes the coverage of the semiconductor/oxide interface and outperforms the usual planar layout in some regimes. This highlights the importance of design in the management of device-to-device variability.