Proposed real-time charge noise measurement via valley state reflectometry
David W. Kanaar, H. Ekmel Ercan, Mark F. Gyure, J. P. Kestner

TL;DR
This paper introduces a novel method for in situ charge noise measurement in silicon quantum dot spin qubits using valley state reflectometry, enabling rapid, real-time noise detection without extra qubits.
Contribution
It proposes a new technique leveraging silicon's valley degree of freedom for fast, in situ charge noise measurement during quantum operations.
Findings
Achieves near-unity signal-to-noise ratio within 1ms measurement time.
Utilizes valley transition dipole coupling to on-chip microwave resonators.
Supports potential for real-time noise monitoring and feedback control.
Abstract
We theoretically propose a method to perform in situ measurements of charge noise during logical operations in silicon quantum dot spin qubits. Our method does not require ancillary spectator qubits but makes use of the valley degree of freedom in silicon. Sharp interface steps or alloy disorder in the well provide a valley transition dipole element that couples to the field of an on-chip microwave resonator, allowing rapid reflectometry of valley splitting fluctuations caused by charge noise. We derive analytic expressions for the signal-to-noise ratio that can be expected and use tight binding simulations to extract the key parameters (valley splitting and valley dipole elements) under realistic disorder. We find that unity signal-to-noise ratio can often be obtained with measurement times below 1ms, faster than typical decoherence times, opening the potential for closed-loop control,…
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
Taxonomy
TopicsElectromagnetic Compatibility and Noise Suppression · Advancements in PLL and VCO Technologies · Low-power high-performance VLSI design
