Automated Design and Optimization of Distributed Filtering Circuits via Reinforcement Learning

TL;DR

This paper introduces an automated reinforcement learning-based approach for designing distributed filter circuits, significantly improving efficiency and quality over traditional methods and existing automation tools like CircuitGNN.

Contribution

The paper presents a novel end-to-end reinforcement learning framework for DFC design, reducing reliance on expert knowledge and outperforming existing automation methods in speed and effectiveness.

Findings

Achieves 8.72% better performance than CircuitGNN.

Execution speed is 2000 times higher on CPU and 241 times higher on GPU.

Demonstrates improved design quality and efficiency in complex and evolving DFCs.

Abstract

Designing distributed filter circuits (DFCs) is complex and time-consuming, involving setting and optimizing multiple hyperparameters. Traditional optimization methods, such as using the commercial finite element solver HFSS (High-Frequency Structure Simulator) to enumerate all parameter combinations with fixed steps and then simulate each combination, are not only time-consuming and labor-intensive but also rely heavily on the expertise and experience of electronics engineers, making it difficult to adapt to rapidly changing design requirements. Additionally, these commercial tools struggle with precise adjustments when parameters are sensitive to numerical changes, resulting in limited optimization effectiveness. This study proposes a novel end-to-end automated method for DFC design. The proposed method harnesses reinforcement learning (RL) algorithms, eliminating the dependence on the design experience of engineers. Thus, it significantly reduces the subjectivity and constraints associated with circuit design. The experimental findings demonstrate clear improvements in design efficiency and quality when comparing the proposed method with traditional engineer-driven methods. Furthermore, the proposed method achieves superior performance when designing complex or rapidly evolving DFCs, highlighting the substantial potential of RL in circuit design automation. In particular, compared to the existing DFC automation design method CircuitGNN, our method achieves an average performance improvement of 8.72%. Additionally, the execution efficiency of our method is 2000 times higher than CircuitGNN on the CPU and 241 times higher on the GPU.