Sensing in Bi-Static ISAC Systems with Clock Asynchronism: A Signal Processing Perspective

TL;DR

This paper reviews the challenges of clock asynchronism in bi-static ISAC systems, highlighting the impact on sensing performance and discussing existing solutions and future research directions.

Contribution

It provides a comprehensive overview of clock asynchronism issues in bi-static ISAC and compares current techniques, offering insights for future research and system development.

Findings

Clock asynchronism causes phase offsets degrading sensing accuracy.

Existing techniques partially mitigate synchronization issues.

Future research should focus on robust synchronization methods.

Abstract

Integrated Sensing and Communication (ISAC) has been identified as a pillar usage scenario for the impending 6G era. Bi-static sensing, a major type of sensing in ISAC, is promising to expedite ISAC in the near future, as it requires minimal changes to the existing network infrastructure. However, a critical challenge for bi-static sensing is clock asynchronism due to the use of different clocks at far-separated transmitters and receivers. This causes the received signal to be affected by time-varying random phase offsets, severely degrading, or even failing, direct sensing. Hence, to effectively enable ISAC, considerable research has been directed toward addressing the clock asynchronism issue in bi-static sensing. This paper provides an overview of the issue and existing techniques developed in an ISAC background. Based on the review and comparison, we also draw insights into the future research directions and open problems, aiming to nurture the maturation of bi-static sensing in ISAC.