IR-Aware ECO Timing Optimization Using Reinforcement Learning

TL;DR

This paper presents a reinforcement learning-based method for IR-drop-aware timing optimization in integrated circuits, improving delay-power tradeoff, runtime, and placement perturbation after physical design.

Contribution

It introduces a novel RL framework with a relational graph convolutional network for gate sizing to fix IR-drop-induced timing violations, outperforming classical algorithms.

Findings

Outperforms LR-only algorithms in delay-power tradeoff

Reduces runtime through fast inference with trained models

Minimizes placement perturbation by sizing fewer cells

Abstract

Engineering change orders (ECOs) in late stages make minimal design fixes to recover from timing shifts due to excessive IR drops. This paper integrates IR-drop-aware timing analysis and ECO timing optimization using reinforcement learning (RL). The method operates after physical design and power grid synthesis, and rectifies IR-drop-induced timing degradation through gate sizing. It incorporates the Lagrangian relaxation (LR) technique into a novel RL framework, which trains a relational graph convolutional network (R-GCN) agent to sequentially size gates to fix timing violations. The R-GCN agent outperforms a classical LR-only algorithm: in an open 45nm technology, it (a) moves the Pareto front of the delay-power tradeoff curve to the left (b) saves runtime over the prior approaches by running fast inference using trained models, and (c) reduces the perturbation to placement by sizing fewer cells. The RL model is transferable across timing specifications and to unseen designs with fine tuning.