Using the Abstract Computer Architecture Description Language to Model AI Hardware Accelerators

TL;DR

This paper demonstrates how to model AI hardware accelerators using the Abstract Computer Architecture Description Language (ACADL), enabling better performance analysis and comparison for selecting suitable accelerators for deep neural networks.

Contribution

It introduces a method to use ACADL for modeling AI accelerators, mapping DNNs onto them, and simulating performance, improving design comparison accuracy.

Findings

ACADL effectively models AI hardware accelerators.

Mapping DNNs onto ACADL models enables performance evaluation.

Simulation semantics provide detailed performance insights.

Abstract

Artificial Intelligence (AI) has witnessed remarkable growth, particularly through the proliferation of Deep Neural Networks (DNNs). These powerful models drive technological advancements across various domains. However, to harness their potential in real-world applications, specialized hardware accelerators are essential. This demand has sparked a market for parameterizable AI hardware accelerators offered by different vendors. Manufacturers of AI-integrated products face a critical challenge: selecting an accelerator that aligns with their product's performance requirements. The decision involves choosing the right hardware and configuring a suitable set of parameters. However, comparing different accelerator design alternatives remains a complex task. Often, engineers rely on data sheets, spreadsheet calculations, or slow black-box simulators, which only offer a coarse understanding of the performance characteristics. The Abstract Computer Architecture Description Language (ACADL) is a concise formalization of computer architecture block diagrams, which helps to communicate computer architecture on different abstraction levels and allows for inferring performance characteristics. In this paper, we demonstrate how to use the ACADL to model AI hardware accelerators, use their ACADL description to map DNNs onto them, and explain the timing simulation semantics to gather performance results.