Neuromorphic Photonic Computing with an Electro-Optic Analog Memory

TL;DR

This paper introduces an integrated neuromorphic photonic system with on-chip analog memory, significantly reducing energy consumption and enabling efficient machine learning tasks like digit recognition.

Contribution

It presents a monolithically integrated photonic circuit with analog memory, demonstrating energy savings and effective in situ training and inference on the MNIST dataset.

Findings

Achieves over 26x power savings compared to traditional architectures.

Maintains >90% inference accuracy with a 100x memory retention-to-latency ratio.

Enables scalable, energy-efficient neuromorphic photonic computing.

Abstract

In neuromorphic photonic systems, device operations are typically governed by analog signals, necessitating digital-to-analog converters (DAC) and analog-to-digital converters (ADC). However, data movement between memory and these converters in conventional von Neumann architectures incur significant energy costs. We propose an analog electronic memory co-located with photonic computing units to eliminate repeated long-distance data movement. Here, we demonstrate a monolithically integrated neuromorphic photonic circuit with on-chip capacitive analog memory and evaluate its performance in machine learning for in situ training and inference using the MNIST dataset. Our analysis shows that integrating analog memory into a neuromorphic photonic architecture can achieve over 26x power savings compared to conventional SRAM-DAC architectures. Furthermore, maintaining a minimum analog memory retention-to-network-latency ratio of 100 maintains >90% inference accuracy, enabling leaky analog memories without substantial performance degradation. This approach reduces reliance on DACs, minimizes data movement, and offers a scalable pathway toward energy-efficient, high-speed neuromorphic photonic computing.