Analog Circuit Sizing Using Machine Learning Based Transistor Circuit Model

TL;DR

This paper introduces a machine learning-based method for fast analog circuit sizing in deep sub-micron CMOS technology, significantly reducing design time while maintaining high accuracy.

Contribution

It presents a novel regression-based approach to predict transistor parameters, eliminating the need for extensive simulations in the design process.

Findings

Achieves over 90% accuracy in transistor sizing predictions.

Reduces design time by more than 97%.

Successfully designs a CFIA with low power and high gain.

Abstract

In this work, a new method for designing an analog circuit for deep sub-micron CMOS fabrication processes is proposed. The proposed method leverages the regression algorithms with the transistor circuit model to size a transistor in 0.18 um technology fast and without using simulation software. Threshold voltage, output resistance, and the product of mobility and oxide capacitance are key parameters in the transistor circuit model to size a transistor. For nano-scale transistors, however, these parameters are nonlinear with respect to electrical and physical characteristics of transistors and circuit simulator is needed to find the value of these parameters and therefore the design time increases. Regression analysis is utilized to predict values of these parameters. We demonstrate the performance of the proposed method by designing a Current Feedback Instrumentational Amplifier (CFIA). We show that the presented method accomplishes higher than 90% accuracy in predicting the desired value of W. It reduces the design time over 97% compared to conventional methods. The designed circuit using the proposed method consumes 5.76 uW power and has a Common Mode Rejection Ratio (CMRR) of 35.83 dB and it results in achieving 8.17 V/V gain.