SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model

TL;DR

This paper investigates using large language models to automate the creation and review of VLSI architecture specifications, aiming to improve efficiency and reduce errors in the chip design process.

Contribution

It introduces a novel application of LLMs for generating and reviewing VLSI specifications, addressing a critical gap in electronic design automation.

Findings

LLMs can generate detailed architecture specifications from scratch.

LLMs can convert RTL code into comprehensive specifications.

Promising results suggest potential for LLMs to enhance IC design workflows.

Abstract

The development of architecture specifications is an initial and fundamental stage of the integrated circuit (IC) design process. Traditionally, architecture specifications are crafted by experienced chip architects, a process that is not only time-consuming but also error-prone. Mistakes in these specifications may significantly affect subsequent stages of chip design. Despite the presence of advanced electronic design automation (EDA) tools, effective solutions to these specification-related challenges remain scarce. Since writing architecture specifications is naturally a natural language processing (NLP) task, this paper pioneers the automation of architecture specification development with the advanced capabilities of large language models (LLMs). Leveraging our definition and dataset, we explore the application of LLMs in two key aspects of architecture specification development: (1) Generating architecture specifications, which includes both writing specifications from scratch and converting RTL code into detailed specifications. (2) Reviewing existing architecture specifications. We got promising results indicating that LLMs may revolutionize how these critical specification documents are developed in IC design nowadays. By reducing the effort required, LLMs open up new possibilities for efficiency and accuracy in this crucial aspect of chip design.