Area and Power Efficient FFT/IFFT Processor for FALCON Post-Quantum Cryptography

TL;DR

This paper presents a highly efficient, low-power FFT/IFFT processor optimized for FALCON post-quantum cryptography, enabling faster and more resource-efficient implementation on edge devices.

Contribution

It introduces a novel hardware processor for FFT/IFFT over the ring tailored for FALCON, with significant area and power savings compared to existing solutions.

Findings

Achieves 2.3× speedup over software on Raspberry Pi 4.

Uses 42% less area and 83% less power than traditional FFT accelerators.

Demonstrates suitability for resource-constrained edge devices.

Abstract

Quantum computing is an emerging technology on the verge of reshaping industries, while simultaneously challenging existing cryptographic algorithms. FALCON, a recent standard quantum-resistant digital signature, presents a challenging hardware implementation due to its extensive non-integer polynomial operations, necessitating FFT over the ring $\mathbb{Q}[x]/(x^n+1)$. This paper introduces an ultra-low power and compact processor tailored for FFT/IFFT operations over the ring, specifically optimized for FALCON applications on resource-constrained edge devices. The proposed processor incorporates various optimization techniques, including twiddle factor compression and conflict-free scheduling. In an ASIC implementation using a 22 nm GF process, the proposed processor demonstrates an area occupancy of 0.15 mm$^2$ and a power consumption of 12.6 mW at an operating frequency of 167 MHz. Since a hardware implementation of FFT/IFFT over the ring is currently non-existent, the execution time achieved by this processor is compared to the software implementation of FFT/IFFT of FALCON on a Raspberry Pi 4 with Cortex-A72, where the proposed processor achieves a speedup of up to 2.3$\times$. Furthermore, in comparison to dedicated state-of-the-art hardware accelerators for classic FFT, this processor occupies 42\% less area and consumes 83\% less power, on average. This suggests that the proposed hardware design offers a promising solution for implementing FALCON on resource-constrained devices.