RandOhm: Mitigating Impedance Side-channel Attacks using Randomized Circuit Configurations

TL;DR

RandOhm introduces a runtime reconfiguration method using FPGA partial reconfiguration to dynamically randomize circuit placement and routing, significantly reducing impedance-based side-channel leakage in cryptographic hardware.

Contribution

This work presents a novel FPGA-based moving target defense against impedance side-channel attacks through real-time circuit randomization using open-source bitstream tools.

Findings

Effective reduction in impedance leakage during attacks

Minimal impact on circuit delay and performance

Validated on AES implementations on 28-nm FPGAs

Abstract

Physical side-channel attacks can compromise the security of integrated circuits. Most physical side-channel attacks (e.g., power or electromagnetic) exploit the dynamic behavior of a chip, typically manifesting as changes in current consumption or voltage fluctuations where algorithmic countermeasures, such as masking, can effectively mitigate them. However, as demonstrated recently, these mitigation techniques are not entirely effective against backscattered side-channel attacks such as impedance analysis. In the case of an impedance attack, an adversary exploits the data-dependent impedance variations of the chip power delivery network (PDN) to extract secret information. In this work, we introduce RandOhm, which exploits a moving target defense (MTD) strategy based on the partial reconfiguration (PR) feature of mainstream FPGAs and programmable SoCs to defend against impedance side-channel attacks. We demonstrate that the information leakage through the PDN impedance could be significantly reduced via runtime reconfiguration of the secret-sensitive parts of the circuitry. Hence, by constantly randomizing the placement and routing of the circuit, one can decorrelate the data-dependent computation from the impedance value. Moreover, in contrast to existing PR-based countermeasures, RandOhm deploys open-source bitstream manipulation tools on programmable SoCs to speed up the randomization and provide real-time protection. To validate our claims, we apply RandOhm to AES ciphers realized on 28-nm FPGAs. We analyze the resiliency of our approach by performing non-profiled and profiled impedance analysis attacks and investigate the overhead of our mitigation in terms of delay and performance.