Conditional Flood Fill Method in Logic Synthesis

TL;DR

This paper presents a new heuristic logic synthesis algorithm based on the Conditional Flood Fill Method, improving efficiency and scalability in optimizing Boolean functions for electronic design automation.

Contribution

It introduces a novel heuristic algorithm with nine new theorems, enhancing logic synthesis performance over traditional methods.

Findings

Significant improvements in computational efficiency

Enhanced scalability for higher-dimension problems

Validated effectiveness through experimental results

Abstract

In the field of Electronic Design Automation (EDA), logic synthesis plays a pivotal role in optimizing hardware resources. Traditional logic synthesis algorithms, such as the Quine-McCluskey method, face challenges in scalability and efficiency, particularly for higher-dimension problems. This paper introduces a novel heuristic algorithm based on Conditional Flood Fill Method aimed at addressing these limitations. Our method employs count-based adjacent element handling and introduces nine new theorems to guide the logic synthesis process. Experimental results validate the efficacy of our approach, showing significant improvements in computational efficiency and scalability compared to existing algorithms. The algorithm holds potential for future advancements in circuit development and Boolean function optimization.