Gemini: Mapping and Architecture Co-exploration for Large-scale DNN Chiplet Accelerators
Jingwei Cai, Zuotong Wu, Sen Peng, Yuchen Wei, Zhanhong Tan, Guiming, Shi, Mingyu Gao, Kaisheng Ma

TL;DR
This paper introduces Gemini, a framework for co-exploring architecture and mapping strategies to optimize large-scale DNN chiplet accelerators, balancing performance, power, and cost in the context of chiplet technology.
Contribution
Gemini provides a novel co-exploration approach specifically designed for large-scale DNN chiplet accelerators, addressing the unique challenges of chiplet integration and interconnect limitations.
Findings
Effective architecture and mapping strategies improve performance and energy efficiency.
Gemini reduces packaging costs and enhances bandwidth utilization.
The framework demonstrates significant gains over baseline approaches.
Abstract
Chiplet technology enables the integration of an increasing number of transistors on a single accelerator with higher yield in the post-Moore era, addressing the immense computational demands arising from rapid AI advancements. However, it also introduces more expensive packaging costs and costly Die-to-Die (D2D) interfaces, which require more area, consume higher power, and offer lower bandwidth than on-chip interconnects. Maximizing the benefits and minimizing the drawbacks of chiplet technology is crucial for developing large-scale DNN chiplet accelerators, which poses challenges to both architecture and mapping. Despite its importance in the post-Moore era, methods to address these challenges remain scarce.
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Code & Models
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
Taxonomy
TopicsInterconnection Networks and Systems · 3D IC and TSV technologies · Low-power high-performance VLSI design
