Hardcaml: An OCaml Hardware Domain-Specific Language for Efficient and Robust Design

TL;DR

Hardcaml is an OCaml-based embedded DSL for hardware design that offers low-level control, type safety, and fast simulation, improving productivity and reducing bugs compared to traditional HDLs.

Contribution

It introduces Hardcaml, a novel OCaml-based hardware DSL that combines low-level control with type safety and fast verification tools, enhancing hardware design workflows.

Findings

Hardcaml enables efficient FPGA design with reduced bug rates.

It provides fast, cycle-accurate simulation and formal verification tools.

Hardcaml successfully competed in the 2022 ZPrize cryptography FPGA track.

Abstract

This paper introduces Hardcaml, an embedded hardware design domain specific language (DSL) implemented in the OCaml programming language. Unlike high level synthesis (HLS), Hardcaml allows for low level control of the underlying hardware for maximum productivity, while abstracting away many of the tedious aspects of traditional hardware definition languages (HDLs) such as Verilog or VHDL. The richness of OCaml's type system combined with Hardcaml's fast circuit elaboration checks reduces the chance of user-introduced bugs and erroneous connections with features like custom type defining, type-safe parameterized modules and elaboration-time bit-width inference and validation. Hardcaml tooling emphasizes fast feedback through simulation, testing, and verification. It includes both a native OCaml cycle-accurate and an event-driven simulator. Unit tests can live in the source code and include digital ASCII waveforms representing the simulator's output. Hardcaml also provides tools for SAT proving and formal verification. Hardcaml is industrially proven, and has been used at Jane Street internally for many large FPGA designs. As a case study we highlight several aspects of our recent Hardcaml submission to the 2022 ZPrize cryptography competition which won 1st place in the FPGA track.