Fast Cell Library Characterization for Design Technology Co-Optimization Based on Graph Neural Networks

TL;DR

This paper introduces a graph neural network model for rapid, accurate cell library characterization in DTCO, significantly reducing simulation time and improving prediction accuracy for various PVT conditions and system-level metrics.

Contribution

The paper presents a novel GNN-based approach for cell library characterization that outperforms traditional methods in speed and accuracy, enabling efficient PPA optimization.

Findings

Achieves mean absolute percentage error (MAPE) ≤ 0.95% in predictions.

Provides 100X speed-up over SPICE simulations.

Accurately predicts system-level metrics with minimal error.

Abstract

Design technology co-optimization (DTCO) plays a critical role in achieving optimal power, performance, and area (PPA) for advanced semiconductor process development. Cell library characterization is essential in DTCO flow, but traditional methods are time-consuming and costly. To overcome these challenges, we propose a graph neural network (GNN)-based machine learning model for rapid and accurate cell library characterization. Our model incorporates cell structures and demonstrates high prediction accuracy across various process-voltage-temperature (PVT) corners and technology parameters. Validation with 512 unseen technology corners and over one million test data points shows accurate predictions of delay, power, and input pin capacitance for 33 types of cells, with a mean absolute percentage error (MAPE) $\le$ 0.95% and a speed-up of 100X compared with SPICE simulations. Additionally, we investigate system-level metrics such as worst negative slack (WNS), leakage power, and dynamic power using predictions obtained from the GNN-based model on unseen corners. Our model achieves precise predictions, with absolute error $\le$3.0 ps for WNS, percentage errors $\le$0.60% for leakage power, and $\le$0.99% for dynamic power, when compared to golden reference. With the developed model, we further proposed a fine-grained drive strength interpolation methodology to enhance PPA for small-to-medium-scale designs, resulting in an approximate 1-3% improvement.