Measurement-driven neural-network training for integrated magnetic tunnel junction arrays
William A. Borders, Advait Madhavan, Matthew W. Daniels, Vasileia, Georgiou, Martin Lueker-Boden, Tiffany S. Santos, Patrick M. Braganca, Mark, D. Stiles, Jabez J. McClelland, and Brian D. Hoskins

TL;DR
This paper demonstrates a measurement-driven, statistics-aware training method for neural networks implemented on magnetic tunnel junction arrays, effectively compensating for hardware defects and variations to maintain high accuracy.
Contribution
It introduces a robust, statistics-aware training approach that accounts for hardware non-idealities, improving neural network performance on defective magnetic tunnel junction arrays.
Findings
Hardware-aware training recovers performance degraded by defects.
Statistics-aware training maintains accuracy across diverse defective dies.
Achieves 2% error increase on MNIST compared to ideal software models.
Abstract
The increasing scale of neural networks needed to support more complex applications has led to an increasing requirement for area- and energy-efficient hardware. One route to meeting the budget for these applications is to circumvent the von Neumann bottleneck by performing computation in or near memory. An inevitability of transferring neural networks onto hardware is that non-idealities such as device-to-device variations or poor device yield impact performance. Methods such as hardware-aware training, where substrate non-idealities are incorporated during network training, are one way to recover performance at the cost of solution generality. In this work, we demonstrate inference on hardware neural networks consisting of 20,000 magnetic tunnel junction arrays integrated on a complementary metal-oxide-semiconductor chips that closely resembles market-ready spin transfer-torque…
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Taxonomy
TopicsAdvanced Memory and Neural Computing · Ferroelectric and Negative Capacitance Devices · Magnetic properties of thin films
