Multiplier Optimization via E-Graph Rewriting

TL;DR

This paper introduces OptiMult, an e-graph based rewriting framework that optimizes multiplier circuits, significantly reducing latency by up to 46%, by exploring trade-offs in multiplier design.

Contribution

The paper presents a novel e-graph based framework for constructing optimized multiplier circuits, enabling customized designs and trade-off exploration.

Findings

Reduced squarer latency by up to 46%

Decreased standard multiplier latency by up to 9%

Demonstrated effectiveness over traditional logic synthesis methods

Abstract

Multiplier circuits account for significant resource usage in datapath-dominated circuit designs, and RTL designers continue to build bespoke hand-crafted multiplication arrays for their particular application. The construction of an optimized multiplier presents trade-offs between pre-processing to generate a smaller array and array reduction. A data structure known as an e-graph has recently been applied to datapath optimization, where the e-graph's ability to efficiently explore trade-offs has been shown to be crucial. We propose an e-graph based rewriting framework to construct optimized multiplier circuits. Such a framework can express alternative multiplier representations and generate customized circuit designs. We demonstrate that the proposed tool, which we call OptiMult, can reduce the latency of a squarer by up to 46% and reduce the latency of a standard multiplier by up to 9% when compared against logic synthesis instantiated components.