Power-balanced Memristive Cryptographic Implementation Against Side Channel Attacks

TL;DR

This paper introduces a novel power-balanced hiding strategy using memristor groups to conceal power consumption in cryptographic circuits, significantly improving security against side-channel attacks.

Contribution

It proposes a new power balancing method for memristive cryptographic logic, ensuring uniform power consumption across all gates during operation.

Findings

Experimental validation shows improved power balance.

T-test confirms significant reduction in power variation.

Enhanced security against side-channel attacks.

Abstract

Memristors, as emerging nano-devices, offer promising performance and exhibit rich electrical dynamic behavior. Having already found success in applications such as neuromorphic and in-memory computing, researchers are now exploring their potential for cryptographic implementations. In this study, we present a novel power-balanced hiding strategy utilizing memristor groups to conceal power consumption in cryptographic logic circuits. Our approach ensures consistent power costs of all 16 logic gates in Complementary-Resistive-Switching-with-Reading (CRS-R) logic family during writing and reading cycles regardless of Logic Input Variable (LIV) values. By constructing hiding groups, we enable an effective power balance in each gate hiding group. Furthermore, experimental validation of our strategy includes the implementation of a cryptographic construction, xor4SBox, using NOR gates. The circuit construction without the hiding strategy and with the hiding strategy undergo T-test analysis, confirming the significant improvement achieved with our approach. Our work presents a substantial advancement in power-balanced hiding methods, offering enhanced security and efficiency in logic circuits.