Advanced Large Language Model (LLM)-Driven Verilog Development: Enhancing Power, Performance, and Area Optimization in Code Synthesis
Kiran Thorat, Jiahui Zhao, Yaotian Liu, Hongwu Peng, Xi Xie, Bin Lei,, Jeff Zhang, Caiwen Ding

TL;DR
This paper presents a novel framework utilizing advanced language models to generate and refine Verilog code, significantly improving power, performance, and area metrics in hardware design through a dual-stage enhancement process.
Contribution
The study introduces a dual-stage refinement protocol for ALM-generated Verilog code, boosting linguistic accuracy and PPA optimization beyond existing methods.
Findings
Achieved 81.37% linguistic accuracy in Verilog synthesis.
Attained 62.0% operational efficacy, outperforming previous techniques.
Demonstrated ALMs' capability in complex hardware design tasks.
Abstract
The increasing use of Advanced Language Models (ALMs) in diverse sectors, particularly due to their impressive capability to generate top-tier content following linguistic instructions, forms the core of this investigation. This study probes into ALMs' deployment in electronic hardware design, with a specific emphasis on the synthesis and enhancement of Verilog programming. We introduce an innovative framework, crafted to assess and amplify ALMs' productivity in this niche. The methodology commences with the initial crafting of Verilog programming via ALMs, succeeded by a distinct dual-stage refinement protocol. The premier stage prioritizes augmenting the code's operational and linguistic precision, while the latter stage is dedicated to aligning the code with Power-Performance-Area (PPA) benchmarks, a pivotal component in proficient hardware design. This bifurcated strategy, merging…
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Taxonomy
TopicsFerroelectric and Negative Capacitance Devices · Parallel Computing and Optimization Techniques · Software Engineering Research
