DREAMPlaceFPGA-MP: An Open-Source GPU-Accelerated Macro Placer for Modern FPGAs with Cascade Shapes and Region Constraints

TL;DR

DREAMPlaceFPGA-MP is an open-source GPU-accelerated macro placer for modern FPGAs that efficiently handles cascade shape constraints and region boundaries, achieving top placement results in recent FPGA macro placement contests.

Contribution

It introduces a GPU-accelerated macro placement method that effectively manages cascade shape and region constraints in FPGA design, advancing open-source FPGA placement tools.

Findings

Achieves top results in MLCAD 2023 FPGA Macro-Placement Contest.

Handles complex cascade shape constraints efficiently.

Provides an open-source tool for FPGA macro placement.

Abstract

FPGA macro placement plays a pivotal role in routability and timing closer to the modern FPGA physical design flow. In modern FPGAs, macros could be subject to complex cascade shape constraints requiring instances to be placed in consecutive sites. In addition, in real-world FPGA macro placement scenarios, designs could have various region constraints that specify boundaries within which certain design instances and macros should be placed. In this work, we present DREAMPlaceFPGA-MP, an open-source GPU-accelerated FPGA macro-placer that efficiently generates legal placements for macros while honoring cascade shape requirements and region constraints. Treating multiple macros in a cascade shape as a large single instance and restricting instances to their respective regions, DREAMPlaceFPGA-MP obtains roughly legal placements. The macros are legalized in multiple steps to efficiently handle cascade shapes and region constraints. Our experimental results demonstrate that DREAMPlaceFPGA-MP is among the top contestants of the MLCAD 2023 FPGA Macro-Placement Contest.