MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design

TL;DR

MasterRTL introduces a novel pre-synthesis estimation framework that converts RTL HDL code into a unified bit-level representation, enabling accurate early-stage PPA predictions for any design.

Contribution

It proposes a new simple operator graph representation and ML models for accurate RTL-stage PPA estimation across diverse designs.

Findings

Achieves higher correlation with actual PPA metrics than previous methods.

Effectively unifies different design styles through the SOG representation.

Demonstrates significant accuracy improvements on a diverse dataset.

Abstract

In modern VLSI design flow, the register-transfer level (RTL) stage is a critical point, where designers define precise design behavior with hardware description languages (HDLs) like Verilog. Since the RTL design is in the format of HDL code, the standard way to evaluate its quality requires time-consuming subsequent synthesis steps with EDA tools. This time-consuming process significantly impedes design optimization at the early RTL stage. Despite the emergence of some recent ML-based solutions, they fail to maintain high accuracy for any given RTL design. In this work, we propose an innovative pre-synthesis PPA estimation framework named MasterRTL. It first converts the HDL code to a new bit-level design representation named the simple operator graph (SOG). By only adopting single-bit simple operators, this SOG proves to be a general representation that unifies different design types and styles. The SOG is also more similar to the target gate-level netlist, reducing the gap between RTL representation and netlist. In addition to the new SOG representation, MasterRTL proposes new ML methods for the RTL-stage modeling of timing, power, and area separately. Compared with state-of-the-art solutions, the experiment on a comprehensive dataset with 90 different designs shows accuracy improvement by 0.33, 0.22, and 0.15 in correlation for total negative slack (TNS), worst negative slack (WNS), and power, respectively.