RapidChiplet: A Toolchain for Rapid Design Space Exploration of Chiplet Architectures

TL;DR

RapidChiplet is a fast prediction toolchain for inter-chiplet interconnect performance, enabling rapid exploration of chiplet architecture design space with minimal accuracy trade-offs.

Contribution

It introduces a novel, efficient toolchain that significantly accelerates ICI performance estimation for chiplet architectures compared to traditional cycle-level simulations.

Findings

Achieves up to 137,682x speedup over cycle-level simulation.

Maintains 0.25%-30.15% accuracy loss.

Facilitates large-scale design space exploration.

Abstract

Chiplet architectures are on the rise as they promise to overcome the scaling challenges of monolithic chips. A key component of such architectures is an efficient inter-chiplet interconnect (ICI). The ICI design space is huge as there are many degrees of freedom such as the number, size, and placement of chiplets, the topology and bandwidth of links, the packaging technology, and many more. While ICI simulators are important to get reliable performance estimates, they are not fast enough to explore hundreds of thousands of design points or to be used as a cost function for optimization algorithms or machine learning models. To address this issue, we present RapidChiplet, a fast and easy to use ICI latency and throughput prediction toolchain. Compared to cycle-level simulations, we trade 0.25%-30.15% of accuracy for 427x-137,682x speedup.