Solving Combinatorial Optimization Problems on Fujitsu Digital Annealer
Yu-Ting Kao, Jia-Le Liao, Hsiu-Chuan Hsu

TL;DR
This paper demonstrates the application of Fujitsu's digital annealer to solve complex combinatorial optimization problems, including number partitioning, graph partitioning, and community detection in power networks, with significant speed and quality improvements.
Contribution
The study formulates new QUBO models for number and graph partitioning problems and showcases the digital annealer's efficiency and effectiveness in solving large-scale real-world optimization tasks.
Findings
Optimal solutions for 6500 variables in under 30 seconds.
Achieved 6% higher modularity than D-wave and simulated annealing.
Successfully identified community structures in power distribution networks.
Abstract
Combinatorial optimization problems are ubiquitous in various disciplines and applications. Many heuristic algorithms have been devoted to solve these types of problems. In order to increase the efficiency for finding the optimal solutions, an application-specific hardware, called digital annealer (DA) has been developed for solving combinatorial optimization problems using quadratic unconstrained binary optimization (QUBO) formulations. In this study, we formulated the number partitioning problem and the graph partitioning problem into QUBO forms and solved such problems with the DA developed by Fujitsu Ltd. The QUBO formulation of the number partitioning problem is fully connected. The DA found the overall runtime for the optimal solution to be less than 30 seconds for 6500 binary variables. For the graph partitioning problem, we adopted modularity as the metric for determining the…
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Taxonomy
TopicsVLSI and FPGA Design Techniques · Low-power high-performance VLSI design · Embedded Systems Design Techniques
