HIDA: A Hierarchical Dataflow Compiler for High-Level Synthesis

TL;DR

HIDA is a hierarchical high-level synthesis framework that automates dataflow architecture generation, significantly improving throughput for neural network implementations on FPGAs compared to existing tools.

Contribution

HIDA introduces a scalable, hierarchical HLS framework with novel dataflow representations and an automated optimizer, advancing the design of efficient dataflow architectures.

Findings

Up to 8.54× higher throughput than SOTA HLS tools.

Achieves 1.29× higher throughput over RTL-based accelerators.

Effectively handles various neural network applications.

Abstract

Dataflow architectures are growing in popularity due to their potential to mitigate the challenges posed by the memory wall inherent to the Von Neumann architecture. At the same time, high-level synthesis (HLS) has demonstrated its efficacy as a design methodology for generating efficient dataflow architectures within a short development cycle. However, existing HLS tools rely on developers to explore the vast dataflow design space, ultimately leading to suboptimal designs. This phenomenon is especially concerning as the size of the HLS design grows. To tackle these challenges, we introduce HIDA, a new scalable and hierarchical HLS framework that can systematically convert an algorithmic description into a dataflow implementation on hardware. We first propose a collection of efficient and versatile dataflow representations for modeling the hierarchical dataflow structure. Capitalizing on these representations, we develop an automated optimizer that decomposes the dataflow optimization problem into multiple levels based on the inherent dataflow hierarchy. Using FPGAs as an evaluation platform, working with a set of neural networks modeled in PyTorch, HIDA achieves up to 8.54$\times$ higher throughput compared to the state-of-the-art (SOTA) HLS optimization tool. Furthermore, despite being fully automated and able to handle various applications, HIDA achieves 1.29$\times$ higher throughput over the SOTA RTL-based neural network accelerators on an FPGA.