Memristor-based hardware and algorithms for higher-order Hopfield optimization solver outperforming quadratic Ising machines

TL;DR

This paper introduces a memristor-based higher-order Hopfield solver that significantly outperforms traditional quadratic Ising machines in solving large Boolean satisfiability problems, offering reductions in time and energy.

Contribution

It presents a novel higher-order Hopfield optimization approach using memristive hardware, overcoming limitations of quadratic Ising models in combinatorial optimization.

Findings

48x reduction in time-to-solution

72x reduction in energy-to-solution

Superior scalability for large problem instances

Abstract

Ising solvers offer a promising physics-based approach to tackle the challenging class of combinatorial optimization problems. However, typical solvers operate in a quadratic energy space, having only pair-wise coupling elements which already dominate area and energy. We show that such quadratization can cause severe problems: increased dimensionality, a rugged search landscape, and misalignment with the original objective function. Here, we design and quantify a higher-order Hopfield optimization solver, with 28nm CMOS technology and memristive couplings for lower area and energy computations. We combine algorithmic and circuit analysis to show quantitative advantages over quadratic Ising Machines (IM)s, yielding 48x and 72x reduction in time-to-solution (TTS) and energy-to-solution (ETS) respectively for Boolean satisfiability problems of 150 variables, with favorable scaling.