Improved Pairwise Measurement-Based Surface Code

TL;DR

This paper introduces a new surface code implementation on a rectangular lattice that uses fewer steps, has a high fault-tolerance threshold, avoids certain errors, and is optimized for Majorana hardware, improving upon previous methods.

Contribution

The paper presents a novel surface code realization with reduced operation steps, enhanced error prevention, and hardware optimization, surpassing prior pairwise measurement-based surface codes.

Findings

Fault-tolerance threshold of approximately 0.66%

Operation period of only 4 steps

Full code distance achieved with boundary conditions

Abstract

We devise a new realization of the surface code on a rectangular lattice of qubits utilizing single-qubit and nearest-neighbor two-qubit Pauli measurements and three auxiliary qubits per plaquette. This realization gains substantial advantages over prior pairwise measurement-based realizations of the surface code. It has a short operation period of 4 steps and our performance analysis for a standard circuit noise model yields a high fault-tolerance threshold of approximately $0.66\% $. The syndrome extraction circuits avoid bidirectional hook errors, so we can achieve full code distance by choosing appropriate boundary conditions. We also construct variants of the syndrome extraction circuits that entirely prevent hook errors, at the cost of larger circuit depth. This achieves full distance regardless of boundary conditions, with only a modest decrease in the threshold. Furthermore, we propose an efficient strategy for dealing with dead components (qubits and measurements) in our surface code realization, which can be adopted more generally for other surface code realizations. This new surface code realization is highly optimized for Majorana-based hardware, accounting for constraints imposed by layouts and the implementation of measurements, making it competitive with the recently proposed Floquet codes.