Sorting it out in Hardware: A State-of-the-Art Survey

TL;DR

This survey reviews recent hardware-based sorting methods, including ASICs, FPGAs, and in-memory solutions, highlighting their challenges, innovations, and future directions in optimizing sorting performance.

Contribution

It provides a comprehensive overview of the latest hardware sorting techniques, categorizing comparison-based and comparison-free approaches, and discusses future design considerations.

Findings

Comparison-based hardware sorting often uses CAS units.

Recent comparison-free solutions reduce complexity.

In-memory sorting addresses memory movement bottlenecks.

Abstract

Sorting is a fundamental operation in various applications and a traditional research topic in computer science. Improving the performance of sorting operations can have a significant impact on many application domains. For high-performance sorting, much attention has been paid to hardware-based solutions. These are often realized with application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs). Recently, in-memory sorting solutions have also been proposed to address the movement cost issue between memory and processing units, also known as Von Neumann bottleneck. Due to the complexity of the sorting algorithms, achieving an efficient hardware implementation for sorting data is challenging. A large body of prior solutions is built on compare-and-swap (CAS) units. These are categorized as comparison-based sorting. Some recent solutions offer comparison-free sorting. In this survey, we review the latest works in the area of hardware-based sorting. We also discuss the recent hardware solutions for partial and stream sorting. Finally, we will discuss some important concerns that need to be considered in the future designs of sorting systems.