Analytical Die-to-Die 3D Placement with Bistratal Wirelength Model and GPU Acceleration

TL;DR

This paper introduces a GPU-accelerated analytical 3D placement framework utilizing a bistratal wirelength model, achieving significant improvements in wirelength, vertical interconnections, and runtime efficiency for heterogeneous 3D ICs.

Contribution

It presents a novel GPU-enabled 3D placement method with a bistratal wirelength model, enhancing performance and efficiency over existing solutions.

Findings

Up to 6.1% wirelength reduction on benchmarks.

Up to 9.8x faster runtime with GPU acceleration.

Outperforms state-of-the-art 3D placers in accuracy and speed.

Abstract

In this paper, we present a new analytical 3D placement framework with a bistratal wirelength model for F2F-bonded 3D ICs with heterogeneous technology nodes based on the electrostatic-based density model. The proposed framework, enabled GPU-acceleration, is capable of efficiently determining node partitioning and locations simultaneously, leveraging the dedicated 3D wirelength model and density model. The experimental results on ICCAD 2022 contest benchmarks demonstrate that our proposed 3D placement framework can achieve up to 6.1% wirelength improvement and 4.1% on average compared to the first-place winner with much fewer vertical interconnections and up to 9.8x runtime speedup. Notably, the proposed framework also outperforms the state-of-the-art 3D analytical placer by up to 3.3% wirelength improvement and 2.1% on average with up to 8.8x acceleration on large cases using GPUs.