Accelerated Modelling of Interfaces for Electronic Devices using Graph Neural Networks

TL;DR

This paper demonstrates how graph neural networks can accelerate the modeling of interfaces in electronic devices, accurately predicting microscopic properties and macroscopic transport characteristics, thus enabling faster device simulations.

Contribution

It introduces a GNN-based approach to efficiently model amorphous heterostructures and predict transistor transport properties, improving scalability over traditional methods.

Findings

GNNs accurately predict atomic forces in amorphous heterostructures.

GNN-based models effectively predict transistor transport characteristics.

The approach enables faster, scalable device modeling.

Abstract

Modern microelectronic devices are composed of interfaces between a large number of materials, many of which are in amorphous or polycrystalline phases. Modeling such non-crystalline materials using first-principles methods such as density functional theory is often numerically intractable. Recently, graph neural networks (GNNs) have shown potential to achieve linear complexity with accuracies comparable to ab-initio methods. Here, we demonstrate the applicability of GNNs to accelerate the atomistic computational pipeline for predicting macroscopic transistor transport characteristics via learning microscopic physical properties. We generate amorphous heterostructures, specifically the HfO$_{2}$-SiO$_{2}$-Si semiconductor-dielectric transistor gate stack, via GNN predicted atomic forces, and show excellent accuracy in predicting transport characteristics including injection velocity for nanoslab silicon channels. This work paves the way for faster and more scalable methods to model modern advanced electronic devices via GNNs.