LLM for SoC Security: A Paradigm Shift
Dipayan Saha, Shams Tarek, Katayoon Yahyaei, Sujan Kumar Saha, Jingbo Zhou, Mark Tehranipoor, Farimah Farahmandi

TL;DR
This paper explores leveraging Large Language Models, specifically GPTs, to enhance the security verification process of complex system-on-chip designs, aiming for more scalable and adaptable security solutions.
Contribution
It introduces a novel approach of integrating LLMs into SoC security verification, addressing current limitations in scalability and effectiveness.
Findings
LLMs can improve SoC security verification efficiency.
Case studies demonstrate practical benefits of LLM integration.
The paper discusses future challenges and prospects in this domain.
Abstract
As the ubiquity and complexity of system-on-chip (SoC) designs increase across electronic devices, the task of incorporating security into an SoC design flow poses significant challenges. Existing security solutions are inadequate to provide effective verification of modern SoC designs due to their limitations in scalability, comprehensiveness, and adaptability. On the other hand, Large Language Models (LLMs) are celebrated for their remarkable success in natural language understanding, advanced reasoning, and program synthesis tasks. Recognizing an opportunity, our research delves into leveraging the emergent capabilities of Generative Pre-trained Transformers (GPTs) to address the existing gaps in SoC security, aiming for a more efficient, scalable, and adaptable methodology. By integrating LLMs into the SoC security verification paradigm, we open a new frontier of possibilities and…
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Taxonomy
TopicsFerroelectric and Negative Capacitance Devices
