Domain Knowledge Graph Construction Via A Simple Checker
Yueling Zeng, Li-C. Wang

TL;DR
This paper introduces a simple checker method leveraging GPT-3.5 to construct domain knowledge graphs from hardware design texts, addressing confidentiality and scalability concerns in semiconductor chip design.
Contribution
It presents an oracle-checker scheme that distills domain expert knowledge using large language models, demonstrating practicality with RISC-V specifications.
Findings
Effective knowledge graph construction from hardware texts.
Utilizes GPT-3.5 for domain knowledge distillation.
Addresses confidentiality and scalability in industry applications.
Abstract
With the availability of large language models, there is a growing interest for semiconductor chip design companies to leverage the technologies. For those companies, deployment of a new methodology must include two important considerations: confidentiality and scalability. In this context, this work tackles the problem of knowledge graph construction from hardware-design domain texts. We propose an oracle-checker scheme to leverage the power of GPT3.5 and demonstrate that the essence of the problem is in distillation of domain expert's background knowledge. Using RISC-V unprivileged ISA specification as an example, we explain key ideas and discuss practicality of our proposed oracle-checker approach.
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Taxonomy
TopicsFerroelectric and Negative Capacitance Devices · Big Data and Digital Economy
