DeMiST: Detection and Mitigation of Stealthy Analog Hardware Trojans

TL;DR

This paper introduces DeMiST, a comprehensive framework for detecting and mitigating stealthy capacitance-based analog hardware Trojans in integrated circuits, addressing limitations of existing methods and enhancing security in the semiconductor supply chain.

Contribution

It presents a novel detection technique for capacitance-based AHTs, analyzes limitations of existing AHTs, proposes a fortified AHT, and develops a two-phase framework for detection and mitigation.

Findings

DeMiST effectively detects stealthy capacitance-based AHTs.

The framework mitigates AHT effects by controlling supply voltage.

Amplified switching activity improves detection accuracy.

Abstract

The global semiconductor supply chain involves design and fabrication at various locations, which leads to multiple security vulnerabilities, e.g., Hardware Trojan (HT) insertion. Although most HTs target digital circuits, HTs can be inserted in analog circuits. Therefore, several techniques have been developed for HT insertions in analog circuits. Capacitance-based Analog Hardware Trojan (AHT) is one of the stealthiest HT that can bypass most existing HT detection techniques because it uses negligible charge accumulation in the capacitor to generate stealthy triggers. To address the charge sharing and accumulation issues, we propose a novel way to detect such capacitance-based AHT in this paper. Secondly, we critically analyzed existing AHTs to highlight their respective limitations. We proposed a stealthier capacitor-based AHT (fortified AHT) that can bypass our novel AHT detection technique by addressing these limitations. Finally, by critically analyzing the proposed fortified AHT and existing AHTs, we developed a robust two-phase framework (DeMiST) in which a synchronous system can mitigate the effects of capacitance-based stealthy AHTs by turning off the triggering capability of AHT. In the first phase, we demonstrate how the synchronous system can avoid the AHT during run-time by controlling the supply voltage of the intermediate combinational circuits. In the second phase, we proposed a supply voltage duty cycle-based validation technique to detect capacitance-based AHTs. Furthermore, DeMiST amplified the switching activity for charge accumulation to such a degree that it can be easily detectable using existing switching activity-based HT detection techniques.