Characterizing the Inter-Core Qubit Traffic in Large-Scale Quantum Modular Architectures

TL;DR

This paper analyzes inter-core qubit traffic in large-scale modular quantum architectures, providing insights into scalability, communication overhead, and optimization strategies for multi-core quantum processors.

Contribution

It offers the first characterization of inter-core qubit traffic in large-scale quantum circuits on multi-core architectures, guiding future optimization and benchmarking.

Findings

Scalability of quantum algorithms demonstrated up to 1000 qubits.

Identification of communication bottlenecks in multi-core quantum systems.

Guidelines for mapping quantum circuits to improve performance.

Abstract

Modular quantum processor architectures are envisioned as a promising solution for the scalability of quantum computing systems beyond the Noisy Intermediate Scale Quantum (NISQ) devices era. Based upon interconnecting tens to hundreds of quantum cores via a quantum intranet, this approach unravels the pressing limitations of densely qubit-packed monolithic processors, mainly by mitigating the requirements of qubit control and enhancing qubit isolation, and therefore enables executing large-scale algorithms on quantum computers. In order to optimize such architectures, it is crucial to analyze the quantum state transfers occurring via inter-core communication networks, referred to as inter-core qubit traffic. This would also provide insights to improve the software and hardware stack for multi-core quantum computers. To this aim, we present a pioneering characterization of the spatio-temporal inter-core qubit traffic in large-scale circuits. The programs are executed on an all-to-all connected multi-core architecture that supports up to around 1000 qubits. We characterize the qubit traffic based on multiple performance metrics to assess the computational process and the communication overhead. Based on the showcased results, we conclude on the scalability of the presented algorithms, provide a set of guidelines to improve mapping quantum circuits to multi-core processors, and lay the foundations of benchmarking large-scale multi-core architectures.