Stencil-HMLS: A multi-layered approach to the automatic optimisation of stencil codes on FPGA

TL;DR

This paper presents Stencil-HMLS, a multi-layered compiler approach integrating MLIR for automatic optimization of stencil codes on FPGAs, achieving significant performance and energy efficiency improvements.

Contribution

It introduces the HLS dialect within MLIR for FPGA programming and demonstrates automated domain-specific optimizations for stencil codes.

Findings

Achieves 14-100× performance improvement over state-of-the-art tools.

Is 14-92× more energy efficient than previous approaches.

Uses PSyclone Fortran DSL for demonstration.

Abstract

The challenges associated with effectively programming FPGAs have been a major blocker in popularising reconfigurable architectures for HPC workloads. However new compiler technologies, such as MLIR, are providing new capabilities which potentially deliver the ability to extract domain specific information and drive automatic structuring of codes for FPGAs. In this paper we explore domain specific optimisations for stencils, a fundamental access pattern in scientific computing, to obtain high performance on FPGAs via automated code structuring. We propose Stencil-HMLS, a multi-layered approach to automatic optimisation of stencil codes and introduce the HLS dialect, which brings FPGA programming into the MLIR ecosystem. Using the PSyclone Fortran DSL, we demonstrate an improvement of 14-100$\times$ with respect to the next best performant state-of-the-art tool. Furthermore, our approach is 14 to 92 times more energy efficient than the next most energy efficient approach.