Inter-temperature Bandwidth Reduction in Cryogenic QAOA Machines

TL;DR

This paper introduces a cryogenic architecture using single-flux quantum logic that significantly reduces bandwidth and heat inflow between cryogenic and room-temperature environments, enhancing the scalability of superconducting quantum computers.

Contribution

It presents the first algorithm-aware, system-level optimization targeting the bandwidth bottleneck in cryogenic quantum systems using a novel counter-based architecture.

Findings

Exponential reduction in bandwidth between cryogenic and room-temperature environments.

Decreased heat inflow and peripheral power consumption.

Improved scalability prospects for superconducting quantum computers.

Abstract

The bandwidth limit between cryogenic and room-temperature environments is a critical bottleneck in superconducting noisy intermediate-scale quantum computers. This paper presents the first trial of algorithm-aware system-level optimization to solve this issue by targeting the quantum approximate optimization algorithm. Our counter-based cryogenic architecture using single-flux quantum logic shows exponential bandwidth reduction and decreases heat inflow and peripheral power consumption of inter-temperature cables, which contributes to the scalability of superconducting quantum computers.