A Resource-efficient FIR Filter Design Based on an RAG Improved Algorithm

TL;DR

This paper presents a resource-efficient FIR filter design using an improved RAG algorithm that reduces hardware resources, enhances speed, and lowers power consumption for digital filter chips.

Contribution

The paper introduces an improved RAG algorithm that optimizes resource utilization and performance in FIR filter hardware design, outperforming existing methods.

Findings

Reduced logic resource utilization

Faster and more stable filter circuits

Lower power consumption across scenarios

Abstract

In modern digital filter chip design, efficient resource utilization is a hot topic. Due to the linear phase characteristics of FIR filters, a pulsed fully parallel structure can be applied to address the problem. To further reduce hardware resource consumption, especially related to multiplication functions, an improved RAG algorithm has been proposed. Filters with different orders and for different algorithms have been compared, and the experimental results show that the improved RAG algorithm excels in terms of logic resource utilization, resource allocation, running speed, and power consumption under various application scenarios. The proposed algorithm introduces a better circuit structure for FIR filters, fully leveraging resource allocation strategies to reduce logic resource consumption. The proposed circuit is faster and more stable, making it suitable for a variety of complex application scenarios.